module nyr(
input        clk,
input        load2,//zhuang_zai_ji_shu_zhi_shang_sheng_yan
input [7:0]  day_in,
input [7:0]  mon_in,
input [7:0]  year_in,

output reg[7:0] day_out,
output reg[7:0] mon_out,
output reg[7:0] year_out

);

reg clk_mon,clk_year;//jin_wei_biao_zhi

//day_out
always@(posedge load2 or posedge clk)
   begin
        if(load2)  
             begin
               day_out=day_in;   
             end
       else if(day_out==8'd29)
             begin
               day_out=0;
               clk_mon=1;
             end
       else 
             begin
                day_out=day_out+1;
                clk_mon=0;
             end

   end


//mon_out
always@(posedge load2 or posedge clk_mon)
   begin
        if(load2)  
             begin
                mon_out=mon_in;   
             end
       else if(mon_out==8'd11)
             begin
               mon_out=0;
               clk_year=1;
             end
       else 
             begin
                mon_out=mon_out+1;
                clk_year=0;
             end

   end
   
//year_out
always@(posedge load2 or posedge clk_year)
   begin
        if(load2)  
             begin
                year_out=year_in;   
             end
       else if(year_out==8'd20)
             begin
               year_out=0;
             end
       else 
             begin
                year_out=year_out+1;
             end

   end
endmodule